In general, point-to-point data communication will require the clock/data frequency to be synchronized between transmitter and receiver ends. For example, with reference to FIG. 1A, a unidirectional transmitter-receiver system 100 is illustrated with transmitter 101 and receiver 102. Data is transmitted in channel 103. Transmitter 101 operates at a frequency derived from reference clock 105, while receiver 102 operates at a frequency derived from reference clock 106. While in an ideal case scenario, both reference clocks 105 and 106 would oscillate at the same frequency F, this ideal case scenario is seldom achievable because of process variations which are inherent in design and manufacture of system 100. Accordingly, reference clock 105 may operate at a reference frequency F+ΔF at which data 103 is transmitted, while reference clock 106 at the receiver end may operate at a reference frequency F, wherein ΔF may be either a positive or negative value. This variation or offset ΔF will prevent data 103 received at receiver 102 to be perfectly synchronized at the receiver end. In high speed data communication even a minor value of ΔF may lead to a high bit error rate which may be unacceptable.
The above problem is also seen in bidirectional communication employing transceivers 111 and 112 as illustrated in system 110 of FIG. 1B. As shown, reference clock 115 at transceiver 111 (comprising transmitter TX1 and receiver RX1) may operate at a frequency F+ΔF while reference clock 116 at transceiver 112 (comprising transmitter TX2 and receiver RX2) may operate at a frequency F. Thus data 113 communicated from transceiver 111 to 112 as well as data 114 communicated transceiver 112 to 111 will suffer from imperfect synchronization.
In both systems 100 and 110, because separate clocks are used as reference clocks at the two ends of data communication, known techniques for synchronization, such as data transmission with embedded clocks, are inefficient and incur expensive design costs because of the frequency offset ΔF. Moreover, the above noted reference clocks are prone to frequency drifts caused by aging, temperature variation, etc, which may further exacerbate the frequency offset. The frequency offset may further degrade system performance and bit error rate by reducing a tolerance margin for clock jitter. Thus, the frequency offset may result in a significant degradation of quality and cost associated with data transmission and reception.
Turning now to FIGS. 2A-C conventional techniques for combating the effects of the frequency offset are illustrated, and their shortcomings will be discussed with reference thereto. Firstly, FIG. 2A illustrates a phase-locked loop (PLL) based closed loop analog clock and data recovery (CDR) system 200. System 200 may be integrated at a receiver end such as receiver 102 of system 100 or in transceivers 111 and 112 of system 110 in order to synchronize received data such as 103, 113 or 114 with the local reference clock. In system 200, received data (data in) is an analog non-return-to-zero (NRZ) signal, which is input to phase detector 20 Phase detector 202 tracks the phase of NRZ data in and generates signals Up and Dn to frequency transformer 203 which in turn generates a response which passes through low pass filter 204 and reaches voltage-controlled oscillator (VCO) 205. The output of VCO 205 is fed back into phase detector 202 to complete loop 207. Loop 207 forms a PLL, which helps align the phase of the local reference clock to that of data in, thus generating a recovered clock at the output of VCO 205. The recovered clock may be buffered by buffer 206 and used by sampler 201 to sample data in to generate the recovered data. System 200 is outdated in its applications as it is configured primarily in the analog domain. Further, while the PLL formed by loop 207 helps in phase alignment, it does not help with synchronizing the frequency of data in with that of the local reference clock. Accordingly, system 200 is not effective in overcoming the aforementioned drawbacks of the frequency offset.
With reference now to FIG. 2B, phase interpolator (PI) based closed loop digital CDR system 210 is illustrated. In system 210, the local reference clock operating at frequency Fref is phase aligned with data in master PLL (MPLL) 218. The reference clock at frequency Fref passes through MPLL 218 and is fed to phase interpolator (P1) 217. PI 217 also receives another input from CDR loop 219 which comprises bang-bang phase detector (!!PD) 214, digital loop filter 214, sigma-delta modulator 215, and decoder 216. In contrast to system 200, bang-bang phase detector 213 generates binary digital outputs Up and Down, which assists in bringing the CDR scheme of system 210 into the digital domain. Using loop CDR 219 (particularly sigma-delta modulator 215 and decoder 216), phase information of the recovered clock is fed to PI 217, whereby PI 217 changes the phase of the recovered clock using phase information along with the reference clock frequency derived from MPLL 218. Received data (data in) is fed through equalizer 211 and the analog data output of equalizer 211 is sampled by sampler 212 using the phase input from PI 217 which enables sampler 212 to sample data in at the correct position and at the correct time. However, if frequency of data in and Fref have a frequency offset, the CDR loop 219 will not be effective. Moreover, if the frequency offset is high, the component blocks of CDR loop 219 will be heavily taxed, thereby leading to performance degradation of system 210.
With reference now to FIG. 2C, a conventional burst mode open loop CDR system 220 is illustrated. System 220 is configured for received data (data in) which may be received in bursts with breaks caused due to events such as channel switches. Local reference clock operating at frequency Fref is input to Phase Frequency Detector (PFD) 221, which outputs Up/Dn signals to frequency transformer (CP) 222. Similar to system 200, frequency tracking block 229 comprises a PLL formed by PFD 221, CP 222, filter 223, shared GVCO 224 and divider 225. Shared GVCO 224 differs from VCO 205 of system 200, in that it includes a gated VCO (GVCO). A GVCO may be configured to gate a VCO, thus enabling control by an edge or level-triggered gating signal. Divider 225 is configured to divide the frequency output of shared GVCO 225 in order to reduce the phase difference by an order N, where N may be a suitably chosen integer or fraction. The clock thus recovered at point 226 from the PLL of frequency tracking block 229 is used to control replica GVCO 227.
In an ideal case, replica GVCO 227 would be designed to be identical to shared GVCO 224, such that the oscillations of replica GVCO 112 may match that of shared GVCO 224 in steady state. However, on-chip fluctuations and process variations may result in minor deviations from this ideal case, causing a frequency offset ΔF2 to appear between oscillation frequencies of shared GVCO 224 and replica GVCO 227. This frequency offset ΔF2 may be in addition to the frequency offset that may already exist between received data (data in) and Fref.
With continuing reference to FIG. 2C, data in is sampled by replica GVCO 227 to generate a recovered clock which controls the clock input of D flip-flop (DFF) 228. Data in which is received as serial data, may then be deserialized by DFF 228 to generate the output, recovered data. However, due to non-idealities noted above, frequency offsets ΔF and ΔF2 may lead to errors and performance degradation of system 220. Further, the jitter tolerance of system 220, which also depends on frequency offsets ΔF and ΔF2, will be correspondingly reduced.
Accordingly, it can be seen that in each of the above-described conventional CDR systems, 200, 210, and 220, the issues related to frequency offsets are insufficiently addressed. Other known techniques attempt to improve the accuracy of the reference clocks using expensive high quality crystal oscillators, which may come at a prohibitively high cost, and yet be insufficient. Some custom designs seeking to incorporate an estimated frequency offset within customized reference clocks in order to compensate for the frequency offset are also known in the art. However, the accuracy of such customized designs severely decreases as the frequency of transmission increases.
Accordingly, there exists a need in the art for CDR systems capable of overcoming the aforementioned problems associated with frequency offsets.